標題: | A 1 V 175 mu W 94.6 dB SNDR 25 kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques |
作者: | Liao, Sheng-Hui Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Delta-sigma modulator;MASH;analog-digital conversion;switched-capacitor circuit |
公開日期: | 1-一月-2018 |
摘要: | A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 mu W from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 1.13 x 0.34 mm(2). |
URI: | http://hdl.handle.net/11536/146171 |
期刊: | 2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) |
顯示於類別: | 會議論文 |