標題: | A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair |
作者: | Chen, Bo-Wei Wang, Jen-Peng Tsai, Chia-Ming 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Comparator;negative resistance;transconductance boosting |
公開日期: | 1-一月-2010 |
摘要: | A high speed, low delay/log(Delta Vin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(Delta Vin) of the comparator is 22ps/dec and consumes 213 mu W at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV. |
URI: | http://hdl.handle.net/11536/146307 |
期刊: | PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) |
起始頁: | 648 |
結束頁: | 651 |
顯示於類別: | 會議論文 |