標題: | Full-Digital High Throughput Design of Adaptive Decision Feedback Equalizers Using Coefficient-Lookahead |
作者: | He, Wen-Quan Lin, Yu-Chun Hung, Jui-Yi Jou, Shyh-Jye 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-一月-2015 |
摘要: | This paper proposes a novel full-digital architecture of adaptive decision feedback equalizer (ADFE) for wireline 2-level pulse amplitude modulation (2-PAM) systems. It is well known that the feedback loop in DFE limits the greatest achievable speed. The proposed scheme begins by deriving coefficient-lookahead concept based on a reasonable assumption, whereupon a preliminary architecture can be implemented using the formula derived. Furthermore, according to channel characteristics, the formula derived can be simplified to break the feedback loop. Finally, the architecture can be easily pipelined and processed in parallel to achieve high throughput rate. Thus, the proposed design is a high speed design with parallel and pipeline architecture. This paper used a TSMC 40 nm CMOS process to fabricate the proposed design with a build-in self-test (BIST) circuit. The measured results show that the throughput rate is up to 16 Gbps. |
URI: | http://hdl.handle.net/11536/146452 |
ISSN: | 2162-7541 |
期刊: | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) |
顯示於類別: | 會議論文 |