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dc.contributor.authorLin, Chia-Lungen_US
dc.contributor.authorLiu, Rong-Jieen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2018-08-21T05:56:43Z-
dc.date.available2018-08-21T05:56:43Z-
dc.date.issued2016-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/146560-
dc.description.abstractLDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.en_US
dc.language.isoen_USen_US
dc.subjectLDPC convolutional codesen_US
dc.subjecthigh throughputen_US
dc.subjectLDPCen_US
dc.subjectoverlapped architectureen_US
dc.subjectdigital signalen_US
dc.titleA 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage337en_US
dc.citation.epage340en_US
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000401471500085en_US
Appears in Collections:Conferences Paper