標題: Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
作者: Lee, Kao-Chi
Wu, Kai-Chiang
Tsai, Chih-Ying
Chao, Mango Chia-Tso
資訊工程學系
電子工程學系及電子研究所
Department of Computer Science
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2017
摘要: As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.
URI: http://hdl.handle.net/11536/146629
ISSN: 1093-0167
期刊: 2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS)
顯示於類別:會議論文