標題: | MULTI-SENSORY COMBINED INTEGRATED LOW POWER TUNABLE-GAIN INTERFACE CIRCUIT |
作者: | Tung, Chun-Te Wen, Kuei-Ann 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | silicon resonator;CMOS MEMS sensor;readout;Gyroscope;Correlated Double Sampling;Tunable-Gain;Interface Circuit |
公開日期: | 1-一月-2017 |
摘要: | This paper presents MEMS multi-sensors with low power tunable-gain interface circuit that can be monolithically integrated in the ASIC compatible standard CMOS process. A high gain ultra-low power sustaining TIA amplifier circuit with PLL compactly has been integrated with the resonator-based core sensing structure. The proposed low-power readout circuit adopts Correlated Double Sampling (CDS) to suppress low frequency noise and compensate DC offset. The gyroscope sensitivity is designed to be 1.8 aF/degrees/sec within +/- 100 degrees/sec. The tunable sensitivity can be adjusted from 28 mV/fF to 224 mV/fF by fully-differential programmable-gain amplifier (PGA). The interface circuit has 61.12dB SNR under 500 KHz sampling rate. |
URI: | http://hdl.handle.net/11536/146680 |
期刊: | 2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017) |
顯示於類別: | 會議論文 |