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dc.contributor.authorWang, Jian-Haoen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2018-08-21T05:56:52Z-
dc.date.available2018-08-21T05:56:52Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn1930-8868en_US
dc.identifier.urihttp://hdl.handle.net/11536/146756-
dc.description.abstractWe analyze the variability of 7T hybrid TFET-MOSFET SRAM and 8T MOSFET SRAM in monolithic 3D technology operating at ultra-low voltage. The impacts of work function variation (WFV) and line edge roughness (LER) on SRAM cell stability, leakage power and performance are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and LER have different impacts on read disturb and V-write,V- 0, which dominate SRAM stability and is determined by the distinct current drive of TFET and MOSFET. The performance is influenced by the different variations of gate capacitance (C-g) under WFV and LER.en_US
dc.language.isoen_USen_US
dc.titleImpacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000408991800022en_US
Appears in Collections:Conferences Paper