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dc.contributor.authorYou, Wei-Xiangen_US
dc.contributor.authorSu, Pinen_US
dc.date.accessioned2018-08-21T05:56:52Z-
dc.date.available2018-08-21T05:56:52Z-
dc.date.issued2017-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/146765-
dc.description.abstractIn this work, with the aid of an analytical and scalable model, we explore the design space for negative-capacitance (NC) FETs with a 2D semiconducting transition-metal-dichalcogenide (TMD) channel with emphasis on the impact of back-gate biasing. Our study indicates that, to mitigate the conflict between subthreshold swing (SS) and hysteresis and to maximize the design space for the NC-TMDFET, a thin buried oxide (BOX) and an adequate reverse back-gate bias can be applied to achieve the optimum design.en_US
dc.language.isoen_USen_US
dc.subjectNegative-capacitance FETen_US
dc.subject2D materialen_US
dc.subjecttransition-metal-dichalcogenideen_US
dc.titleDesign Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM)en_US
dc.citation.spage136en_US
dc.citation.epage137en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000409022100056en_US
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