標題: Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures
作者: You, Wei-Xiang
Su, Pin
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 2 D semiconductors;double gate (DG);ferroelectric field effect transistor (FET);Landau-Khalatnikov (L-K) equation;metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance (NC) FET (NCFET);semiconductor-on-insulator (SOI);transitionmetal-dichalcogenide (TMD)
公開日期: 1-十月-2018
摘要: With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator(SOI) and double-gate (DG) metal-ferroelectric-insulator-semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications.
URI: http://dx.doi.org/10.1109/TED.2018.2866125
http://hdl.handle.net/11536/148188
ISSN: 0018-9383
DOI: 10.1109/TED.2018.2866125
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 65
起始頁: 4196
結束頁: 4201
顯示於類別:期刊論文