完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tsai, Tsung-Ying | en_US |
dc.contributor.author | Lee, Ren-Jie | en_US |
dc.contributor.author | Chin, Ching-Yu | en_US |
dc.contributor.author | Kuan, Chung-Yi | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.contributor.author | Kajitani, Yoji | en_US |
dc.date.accessioned | 2018-08-21T05:56:53Z | - |
dc.date.available | 2018-08-21T05:56:53Z | - |
dc.date.issued | 2011-01-01 | en_US |
dc.identifier.issn | 1530-1591 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146781 | - |
dc.description.abstract | Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the pack-ages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. Previous works in escape routing are not likely to be used due to this nature, in this work, we describe this fixed ordering boundary pin escaping problem, and propose a practical approach to solve it. Not only can we have a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. our approach has different feature compared with conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirement and wire shape resemblance for high speed signal routes on board. Our results show that we can utilize routing resource very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board busses as well. | en_US |
dc.language.iso | en_US | en_US |
dc.title | On Routing Fixed Escaped Boundary Pins for High Speed Boards | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE) | en_US |
dc.citation.spage | 455 | en_US |
dc.citation.epage | 460 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000410278900083 | en_US |
顯示於類別: | 會議論文 |