標題: Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory
作者: Fan, Chia-Chi
Chiu, Yu-Chien
Liu, Chien
Liou, Guan-Lin
Lai, Wen-Wei
Chen, Yi-Ru
Chang, Tun-Jen
Chen, Wan-Hsin
Cheng, Chun-Hu
Chang, Chun-Yen
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2017
摘要: In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.
URI: http://hdl.handle.net/11536/146935
ISSN: 2161-4636
期刊: 2017 SILICON NANOELECTRONICS WORKSHOP (SNW)
起始頁: 101
結束頁: 102
Appears in Collections:Conferences Paper