Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chiang, Chun	en_US
dc.contributor.author	Chang, Ping-Chen	en_US
dc.contributor.author	Chao, Mei-Ling	en_US
dc.contributor.author	Tang, Tien-Hao	en_US
dc.contributor.author	Su, Kuan-Cheng	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.date.accessioned	2018-08-21T05:57:09Z	-
dc.date.available	2018-08-21T05:57:09Z	-
dc.date.issued	2017-01-01	en_US
dc.identifier.issn	1946-1550	en_US
dc.identifier.uri	http://hdl.handle.net/11536/147120	-
dc.description.abstract	According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V-BD) and low holding voltage (V-h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (V-t1=8.1V) without suffering from low V-BD and latch-up issues.	en_US
dc.language.iso	en_US	en_US
dc.title	Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000426989100171	en_US
顯示於類別：	會議論文