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dc.contributor.authorChen, Hsiu-Chien_US
dc.contributor.authorKho, Yi-Tungen_US
dc.contributor.authorHuang, Yen-Junen_US
dc.contributor.authorHsieh, Yu-Shengen_US
dc.contributor.authorChang, Yao-Jenen_US
dc.contributor.authorTang, Ya-Shengen_US
dc.contributor.authorYu, Ting-Yangen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:57:12Z-
dc.date.available2018-08-21T05:57:12Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn2150-5934en_US
dc.identifier.urihttp://hdl.handle.net/11536/147172-
dc.description.abstractIn this work, a particular ultra-thin buffer layer (UBL) with various thickness ranging from 10 nm to 100 nm and different materials including Co, Ni, Pd and Ti is inserted between Cu/Sn to delay the interdiffusion prior to eutectic bonding. The efficacy of the buffer layer and the bonding quality are systematically conferred using microstructure imaging, material analysis, and electrical performance. In addition to symmetric Cu/Sn bonding with UBL, an asymmetric Cu/Sn-Cu bonding which is proposed to relieve the heat enhanced interdiffUsion issues thereby enhancing the reliability performance is demonstrated with the assistance of UBL technology.en_US
dc.language.isoen_USen_US
dc.titleDevelopment and Investigation of Ultra-Thin Buffer Layers Used in Symmetric Cu/Sn Bonding and Asymmetric Cu/Sn-Cu Bonding for Advanced 3D Integration Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 12TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT)en_US
dc.citation.spage85en_US
dc.citation.epage88en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000427990200012en_US
Appears in Collections:Conferences Paper