Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, Yi-Min | en_US |
dc.contributor.author | Yang, Chi-Heng | en_US |
dc.contributor.author | Hsu, Chih-Hsiang | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:20:48Z | - |
dc.date.available | 2014-12-08T15:20:48Z | - |
dc.date.issued | 2011-10-01 | en_US |
dc.identifier.issn | 1549-7747 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2011.2161704 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/14782 | - |
dc.description.abstract | According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Bose-Chaudhuri-Hochquenghem (BCH) code | en_US |
dc.subject | Chien search | en_US |
dc.subject | error correction code | en_US |
dc.subject | NAND Flash memory | en_US |
dc.title | A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSII.2011.2161704 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 58 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 682 | en_US |
dc.citation.epage | 686 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000296009700014 | - |
dc.citation.woscount | 2 | - |
Appears in Collections: | Articles |
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