標題: | A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices |
作者: | Lin, Yi-Min Yang, Chi-Heng Hsu, Chih-Hsiang Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Bose-Chaudhuri-Hochquenghem (BCH) code;Chien search;error correction code;NAND Flash memory |
公開日期: | 1-十月-2011 |
摘要: | According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design. |
URI: | http://dx.doi.org/10.1109/TCSII.2011.2161704 http://hdl.handle.net/11536/14782 |
ISSN: | 1549-7747 |
DOI: | 10.1109/TCSII.2011.2161704 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 58 |
Issue: | 10 |
起始頁: | 682 |
結束頁: | 686 |
顯示於類別: | 期刊論文 |