標題: Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications
作者: Yao, Jing-Neng
Lin, Yueh-Chin
Hsu, Heng-Tung
Yang, Kai-Chun
Hsu, Hisang-Hua
Sze, Simon M.
Chang, Edward Yi
材料科學與工程學系
光電系統研究所
影像與生醫光電研究所
電子工程學系及電子研究所
國際半導體學院
Department of Materials Science and Engineering
Institute of Photonic System
Institute of Imaging and Biomedical Photonics
Department of Electronics Engineering and Institute of Electronics
International College of Semiconductor Technology
關鍵字: InAs;E-mode;sidewall etch;non-alloyed
公開日期: 1-Jan-2018
摘要: In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an I-on/I-off ratio of 1.34 x 10(4), a G(m,max)/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 x 10(-5) A/mm at V-DS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
URI: http://dx.doi.org/10.1109/JEDS.2018.2853547
http://hdl.handle.net/11536/147919
ISSN: 2168-6734
DOI: 10.1109/JEDS.2018.2853547
期刊: IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume: 6
起始頁: 797
結束頁: 802
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