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dc.contributor.authorChao, TSen_US
dc.contributor.authorChu, CHen_US
dc.contributor.authorWang, CFen_US
dc.contributor.authorHo, KJen_US
dc.contributor.authorLei, TFen_US
dc.contributor.authorLee, CLen_US
dc.date.accessioned2019-04-02T06:00:52Z-
dc.date.available2019-04-02T06:00:52Z-
dc.date.issued1996-12-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.35.6003en_US
dc.identifier.urihttp://hdl.handle.net/11536/149405-
dc.description.abstractIn this paper, a comprehensive study of gate engineering to suppress the penetration of boron in p-type metaloxide-semiconductor held-effect transistor (MOSFET) with the p(+)-poly-Si-gate is reported. Four types of poly-Si gate structure, two types of gate dielectrics were investigated to suppress the boron penetration. Among the different gate structures, the stacked amorphous silicon structure was found to be the most effective way to retard the boron penetration. N2O oxide exhibited a better retarding of the boron diffusion as compared with the O-2 oxide. It was found that a combination of stacked amorphous silicon with N2O oxide is the most effective way to suppress the boron penetration. Thermal stability, oxide integrity, and D-it of this sample are superior to all the other samples.en_US
dc.language.isoen_USen_US
dc.subjectboronen_US
dc.subjectpenetrationen_US
dc.subjectstack poly-Sien_US
dc.subjectN2O oxideen_US
dc.titleSuppression of boron penetration in BF2+-implanted poly-Si gateen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.35.6003en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume35en_US
dc.citation.spage6003en_US
dc.citation.epage6007en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996WF47900017en_US
dc.citation.woscount3en_US
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