完整後設資料紀錄
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dc.contributor.authorYen, LHen_US
dc.contributor.authorHuang, TLen_US
dc.date.accessioned2019-04-02T05:59:11Z-
dc.date.available2019-04-02T05:59:11Z-
dc.date.issued1997-05-25en_US
dc.identifier.issn0743-7315en_US
dc.identifier.urihttp://dx.doi.org/10.1006/jpdc.1997.1330en_US
dc.identifier.urihttp://hdl.handle.net/11536/149656-
dc.description.abstractThis paper establishes the necessary and sufficient condition for a correct clock resetting such that the functionality of vector clocks can be preserved. A clock reset protocol is presented with its applicability and limitation discussed. Our result indicates that for some applications, the potential of clock overflow can be completely prevented by carefully choosing the condition for initiating the clock reset protocol. (C) 1997 Academic Press.en_US
dc.language.isoen_USen_US
dc.titleResetting vector clocks in distributed systemsen_US
dc.typeArticleen_US
dc.identifier.doi10.1006/jpdc.1997.1330en_US
dc.identifier.journalJOURNAL OF PARALLEL AND DISTRIBUTED COMPUTINGen_US
dc.citation.volume43en_US
dc.citation.spage15en_US
dc.citation.epage20en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1997XY10100002en_US
dc.citation.woscount3en_US
顯示於類別:期刊論文