完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yen, LH | en_US |
dc.contributor.author | Huang, TL | en_US |
dc.date.accessioned | 2019-04-02T05:59:11Z | - |
dc.date.available | 2019-04-02T05:59:11Z | - |
dc.date.issued | 1997-05-25 | en_US |
dc.identifier.issn | 0743-7315 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1006/jpdc.1997.1330 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/149656 | - |
dc.description.abstract | This paper establishes the necessary and sufficient condition for a correct clock resetting such that the functionality of vector clocks can be preserved. A clock reset protocol is presented with its applicability and limitation discussed. Our result indicates that for some applications, the potential of clock overflow can be completely prevented by carefully choosing the condition for initiating the clock reset protocol. (C) 1997 Academic Press. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Resetting vector clocks in distributed systems | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1006/jpdc.1997.1330 | en_US |
dc.identifier.journal | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING | en_US |
dc.citation.volume | 43 | en_US |
dc.citation.spage | 15 | en_US |
dc.citation.epage | 20 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:A1997XY10100002 | en_US |
dc.citation.woscount | 3 | en_US |
顯示於類別: | 期刊論文 |