一個低延遲的全域非同步區域同步電路之界面

Abstract

GALS藉由非同步的溝通方式，在模組之間提供了一個可靠的溝通方式，因此GALS可被用在系統單晶片設計上。但是這種非同步的介面所造成的延遲可能會導致效能的減少，因為當溝通發生時，並不會有任何的產出。因此如何減少GALS介面的延遲是很重要的。 我們使用Verilog實作了一個更快，更小的可延伸時脈GALS介面，並且用TSMC 0.13μm 元件庫做合成。最後，新設計的面積與速度會與其他設計做比較。同時，我們可在模組與模組之間的資料傳輸路徑上多加一個先入先出的儲存元件，這可避免傳送端長時間等待的情形。這些方法減少了模組間溝通的時間，GALS系統的效能也因此獲得提升。

GALS can be used in SoC design because GALS provide a reliable communication by asynchronous channel between different modules. The latency of GALS interface is a problem which could cause performance degradation because there is no throughput when the communication occurs. Thus how to reduce the latency of GALS interface is significant. A faster, smaller stretchable clock GALS interface is implemented with Verilog and synthesized with TSMC 0.13μm cell library. The area and speed of the new design are compared to other designs finally. Also a Muller-pipeline FIFO storage element can be added between the data transmission path to avoid long time waiting of sender. These schemes decrease the communication time of modules thus improve the performance of GALS system.