High-Performance GaN MOSFET With High-k LaAlO(3)/SiO(2) Gate Dielectric

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tsai, C. Y.	en_US
dc.contributor.author	Wu, T. L.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.date.accessioned	2014-12-08T15:21:10Z	-
dc.date.available	2014-12-08T15:21:10Z	-
dc.date.issued	2012-01-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2011.2172911	en_US
dc.identifier.uri	http://hdl.handle.net/11536/15019	-
dc.description.abstract	Using a high-k LaAlO(3)/SiO(2) gate dielectric, the recessed-gate GaN MOSFET has a low threshold voltage (V(t)) of 0.1 V, low on-resistance (R(on)) of 13.5 Omega . mm, high breakdown voltage of 385 V, high transconductance (g(m)) of 136 mS/mm, and record-best normalized drive current (mu C(ox)) of 172 mu A/V(2). Such excellent device integrity is due to the small capacitance equivalent thickness of 3.0 nm, using a high-k gate dielectric and recessed-gate etching.	en_US
dc.language.iso	en_US	en_US
dc.title	High-Performance GaN MOSFET With High-k LaAlO(3)/SiO(2) Gate Dielectric	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2011.2172911	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	33	en_US
dc.citation.issue	1	en_US
dc.citation.spage	35	en_US
dc.citation.epage	37	en_US
dc.contributor.department	電機工程學系	zh_TW
dc.contributor.department	Department of Electrical and Computer Engineering	en_US
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