標題: | A 723-MHz 17.2-mW CMOS programmable counter |
作者: | Chang, HH Wu, JC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | CMOS digital integrated circuits;flip-flop circuits;logic design;phase-locked loops;programmable circuits |
公開日期: | 1-十月-1998 |
摘要: | A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW. |
URI: | http://dx.doi.org/10.1109/4.720407 http://hdl.handle.net/11536/150293 |
ISSN: | 0018-9200 |
DOI: | 10.1109/4.720407 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 33 |
起始頁: | 1572 |
結束頁: | 1575 |
顯示於類別: | 期刊論文 |