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dc.contributor.authorChang, HHen_US
dc.contributor.authorWu, JCen_US
dc.date.accessioned2019-04-02T05:59:24Z-
dc.date.available2019-04-02T05:59:24Z-
dc.date.issued1998-10-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/4.720407en_US
dc.identifier.urihttp://hdl.handle.net/11536/150293-
dc.description.abstractA high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed, Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-mu m CMOS technology. The active die area is 480 x 100 mu m. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW.en_US
dc.language.isoen_USen_US
dc.subjectCMOS digital integrated circuitsen_US
dc.subjectflip-flop circuitsen_US
dc.subjectlogic designen_US
dc.subjectphase-locked loopsen_US
dc.subjectprogrammable circuitsen_US
dc.titleA 723-MHz 17.2-mW CMOS programmable counteren_US
dc.typeArticleen_US
dc.identifier.doi10.1109/4.720407en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume33en_US
dc.citation.spage1572en_US
dc.citation.epage1575en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000076051800016en_US
dc.citation.woscount18en_US
Appears in Collections:Articles