標題: | Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO2 Charge Trapping Layer |
作者: | Chen, Lun-Jyun Wu, Yung-Chun Chiang, Ji-Hong Hung, Min-Feng Chang, Chin-Wei Su, Po-Wen 交大名義發表 National Chiao Tung University |
關鍵字: | Hafnium Oxide (HfO2);nanowire;nonvolatile memory (NVM);pi-gate;polycrystalline silicon (poly-Si);thin-film transistor (TFT) |
公開日期: | 1-Mar-2011 |
摘要: | This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO2 charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 mu s. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pigate NWs poly-Si TFT NVM with a Si3N4 charge-trapping layer was also fabricated. Since HfO2 has a deeper conduction band than Si3N4, the device with the HfO2 charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si3N4 charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO2 charge-trapping layer to undergo more P/E cycles than that with the Si3N4 charge-trapping layer. |
URI: | http://dx.doi.org/10.1109/TNANO.2009.2038479 http://hdl.handle.net/11536/150305 |
ISSN: | 1536-125X |
DOI: | 10.1109/TNANO.2009.2038479 |
期刊: | IEEE TRANSACTIONS ON NANOTECHNOLOGY |
Volume: | 10 |
起始頁: | 260 |
結束頁: | 265 |
Appears in Collections: | Articles |