標題: A maskable memory architecture for rank-order filtering
作者: Lin, MC
Dung, LR
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 1-Jan-2004
摘要: This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can. benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.
URI: http://hdl.handle.net/11536/150669
期刊: PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY
起始頁: 453
結束頁: 456
Appears in Collections:Conferences Paper