完整後設資料紀錄
DC 欄位語言
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.contributor.authorLee, Pei-Yuen_US
dc.date.accessioned2019-04-02T06:04:30Z-
dc.date.available2019-04-02T06:04:30Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2159-3469en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ISVLSI.2018.00134en_US
dc.identifier.urihttp://hdl.handle.net/11536/150728-
dc.description.abstractAs designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can timing macro models be made compact and accurate? How do state-of-the art works maintain model accuracy, model size, model generation performance, and model usage performance? Finally, future research directions on timing macro modeling are identified.en_US
dc.language.isoen_USen_US
dc.subjectStatic timing analysisen_US
dc.subjecthierarchical timing analysisen_US
dc.subjecttiming macro modelingen_US
dc.subjectinterface logic modelen_US
dc.subjectextracted timing modelen_US
dc.titleTiming Macro Modeling for Efficient Hierarchical Timing Analysisen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ISVLSI.2018.00134en_US
dc.identifier.journal2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)en_US
dc.citation.spage714en_US
dc.citation.epage714en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000443443500124en_US
dc.citation.woscount0en_US
顯示於類別:會議論文