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dc.contributor.authorPatyal, Abhisheken_US
dc.contributor.authorPan, Po-Chengen_US
dc.contributor.authorAsha, K. A.en_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorChi, Hao-Yuen_US
dc.contributor.authorLiu, Chien-Nanen_US
dc.date.accessioned2019-04-02T06:04:25Z-
dc.date.available2019-04-02T06:04:25Z-
dc.date.issued2018-01-01en_US
dc.identifier.urihttp://dx.doi.org/10.1145/3195970.3195990en_US
dc.identifier.urihttp://hdl.handle.net/11536/150756-
dc.description.abstractModern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.en_US
dc.language.isoen_USen_US
dc.subjectAnalog Layout Synthesisen_US
dc.subjectPCP Constraintsen_US
dc.subjectSequence Pairen_US
dc.titleAnalog Placement with Current Flow and Symmetry Constraints using PCP-SPen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/3195970.3195990en_US
dc.identifier.journal2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000446034500004en_US
dc.citation.woscount0en_US
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