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dc.contributor.authorLo, Rogeren_US
dc.contributor.authorLue, Hang-Tingen_US
dc.contributor.authorChen, Weichenen_US
dc.contributor.authorDu, Pei-Yingen_US
dc.contributor.authorHsu, Tzu-Hsuanen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.authorWang, Keh-Chungen_US
dc.contributor.authorLu, Chih-Yuanen_US
dc.date.accessioned2019-04-02T06:04:53Z-
dc.date.available2019-04-02T06:04:53Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2330-7978en_US
dc.identifier.urihttp://hdl.handle.net/11536/150785-
dc.description.abstractA novel dual-channel 3D NAND device was proposed previously [1]. In addition to the N- and P-channel read operations, such device can also perform a special "thyristor mode" which possesses super steep subthreshold slope (S.S. similar to 0). In this work, we studied 4 different types of read methods with the same device, which are normal N- and P-channel read, and thyristor-mode N- and P-channel read, respectively. These 4 different read methods can be carried out by just simply changing the bias arrangements of wordlines so that the IdVg curves can behave differently. An interesting finding is that the Vt window of PIE cycling and retention are quite different among these sensing methods. It may provide a new methodology to understand the charge storage mechanisms. 'this work provides a comprehensive study for understanding the operation physics of this novel device.en_US
dc.language.isoen_USen_US
dc.titleStudy of Thyristor-Mode Dual-Channel NAND Flash Devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW)en_US
dc.citation.spage27en_US
dc.citation.epage30en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000448849300006en_US
dc.citation.woscount0en_US
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