標題: | Implementation of Functionally Complete Boolean Logic and 8-bit Adder in CMOS Compatible 1T1R RRAMs for In-Memory Computing |
作者: | Wang, Z. R. Li, Y. Su, Y. T. Zhou, Y. X. Yin, K. S. Cheng, L. Chang, T. C. Xue, K. H. Sze, S. M. Miao, X. S. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | In-memory computing;RRAM;Functionally complete Boolean logic;8-bit adder |
公開日期: | 1-一月-2018 |
摘要: | RRAM is a promising candidate to construct in-memory computing architecture which can break through the von Neumann bottleneck. Taking advantage of the CMOS compatible 1T1R RRAM, functionally complete Boolean logics can be realized within two steps in a single unit that can suppress sneak pass problem and avoid cascading problem partially. In addition, an 8-bit pre-calculation adder with low computation complexity is designed and demonstrated experimentally to verify the feasibility and efficiency of 1T1R based in-memory computing architecture, which is applicable to future energy-efficient information processing systems. |
URI: | http://hdl.handle.net/11536/150787 |
ISSN: | 2330-7978 |
期刊: | 2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW) |
起始頁: | 62 |
結束頁: | 65 |
顯示於類別: | 會議論文 |