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dc.contributor.authorKu, Fang-Juen_US
dc.contributor.authorWu, Tung-Yuen_US
dc.contributor.authorLiao, Yen-Chinen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorWong, Wing Hungen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2019-04-02T06:04:51Z-
dc.date.available2019-04-02T06:04:51Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/150808-
dc.description.abstractThis paper presents an implementation of an energy efficient hit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-Hag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm IP9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.en_US
dc.language.isoen_USen_US
dc.subjectbig data analysisen_US
dc.subjectbit-planeen_US
dc.subjecthardware architectureen_US
dc.subjectBayesian sequential partitionen_US
dc.titleA 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000450113800042en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper