標題: | A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS |
作者: | Ku, Fang-Ju Wu, Tung-Yu Liao, Yen-Chin Chang, Hsie-Chia Wong, Wing Hung Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | big data analysis;bit-plane;hardware architecture;Bayesian sequential partition |
公開日期: | 1-Jan-2018 |
摘要: | This paper presents an implementation of an energy efficient hit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-Hag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm IP9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query. |
URI: | http://hdl.handle.net/11536/150808 |
ISSN: | 2474-2724 |
期刊: | 2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) |
Appears in Collections: | 會議論文 |