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dc.contributor.authorChen, Li-Chinen_US
dc.contributor.authorHuang, Chien-Chiaen_US
dc.contributor.authorChang, Yao-Linen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2019-04-02T06:04:51Z-
dc.date.available2019-04-02T06:04:51Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/150809-
dc.description.abstractThe mutability of a circuit is a critical challenge due to the complexity of design rules. Global routing produces a congestion map on a coarse grid and feeds the results to the placer to optimize the design for reducing detailed-route DRC violations. However, there is a growing gap between global routing and the actual violations in detailed routing. This miscorrelation may end up unroutable for back-end detailed routing. In this work, a methodology as well as the framework How based on machine learning technique is proposed to effectively predict detailed routing violations. After extracting appropriate features from placement, fast global routing and detailed routing violations, we use support vector machine techniques to train the prediction model, different from regression framework. We then also develop a prediction model for DRC violation density which can be integrated into placers. Experimental results show that the proposed approach can effectively forecast routability during placement stage.en_US
dc.language.isoen_USen_US
dc.titleA Learning-Based Methodology for Routability Prediction in Placementen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000450113800049en_US
dc.citation.woscount0en_US
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