完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTarntair, FGen_US
dc.contributor.authorWang, CCen_US
dc.contributor.authorHong, WKen_US
dc.contributor.authorHuang, HKen_US
dc.contributor.authorCheng, HCen_US
dc.date.accessioned2019-04-02T06:04:19Z-
dc.date.available2019-04-02T06:04:19Z-
dc.date.issued1998-01-01en_US
dc.identifier.issn0272-9172en_US
dc.identifier.urihttp://dx.doi.org/10.1557/PROC-509-15en_US
dc.identifier.urihttp://hdl.handle.net/11536/150946-
dc.description.abstractA triode structure of chimney-shaped field emitter arrays is proposed in this article. This triode structure includes the chimney-shaped emitter, thermal oxidation dioxide, and the plateau-shaped singlecrystalline silicon gate electrode. For the application of the matrix-addressable and large area flat panel display, the uniform structure of the emitters and the yield become critical manufacturing issues when attempting to control nano-meter size features. The uniformity and yield of the chimney-shaped emitters are very well controlled. The nano-sized gate-to-emitter separations can be created by the changing thickness of the insulator. The uniformity of the insulator and emitter material can be controlled within 3% which can be obtained by most large area thin film deposition tools, not by photolithography.en_US
dc.language.isoen_USen_US
dc.titleChimney-shaped and plateau-shaped gate electrode field emission arraysen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1557/PROC-509-15en_US
dc.identifier.journalMATERIALS ISSUES IN VACUUM MICROELECTRONICSen_US
dc.citation.volume509en_US
dc.citation.spage15en_US
dc.citation.epage20en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000075974000003en_US
dc.citation.woscount0en_US
顯示於類別:會議論文