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dc.contributor.authorChan, Cheng-Chien_US
dc.contributor.authorYu, Yen-Tingen_US
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.date.accessioned2014-12-08T15:21:18Z-
dc.date.available2014-12-08T15:21:18Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-61284-914-0en_US
dc.identifier.issn1948-3295en_US
dc.identifier.urihttp://hdl.handle.net/11536/15110-
dc.description.abstractDuring the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, bandwidth, footprint, and heterogeneous technology mixing. However, before adopting the 3D design strategy, this study seeks to understand how much cost is required to trade these benefits. This paper proposes a 3D IC cost evaluation framework based on fast tier number estimation Using a reformulated Rent's rule, this study efficiently determines the number k of tiers to minimize the through-silicon via count and then automatically partitions a gate-level netlist into k tiers to minimize the total cost. This study conducted experiments on eight industrial test cases to show cost efficiency and effectiveness. Moreover, results prove that the reformulated Rent's rule indicates a strong correlation between the tier number and through-silicon via usage.en_US
dc.language.isoen_USen_US
dc.subject3D ICen_US
dc.subjectTSVen_US
dc.subjectcost evaluationen_US
dc.subjectpartitioningen_US
dc.title3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)en_US
dc.citation.spage50en_US
dc.citation.epage55en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000299054300008-
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