Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 張翼 | zh_TW |
| dc.contributor.author | 劉世謙 | zh_TW |
| dc.contributor.author | 黃崇愷 | zh_TW |
| dc.contributor.author | 吳佳勳 | zh_TW |
| dc.contributor.author | 韓秉承 | zh_TW |
| dc.contributor.author | 林岳欽 | zh_TW |
| dc.contributor.author | 謝廷恩 | zh_TW |
| dc.date.accessioned | 2019-04-11T06:20:31Z | - |
| dc.date.available | 2019-04-11T06:20:31Z | - |
| dc.date.issued | 2018-07-01 | en_US |
| dc.identifier.govdoc | H01L029/12 | en_US |
| dc.identifier.govdoc | H01L029/06 | en_US |
| dc.identifier.govdoc | H01L029/772 | en_US |
| dc.identifier.govdoc | H01L021/8252 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/151477 | - |
| dc.description.abstract | 一種半導體裝置，包含：基材、通道層、阻障層、凹槽、電荷陷阱層、鐵電材料、閘極、源極和汲極。通道層配置於基材上；阻障層配置於通道層上，阻障層具有凹槽，且凹槽下方之阻障層具有一厚度；汲極和源極配置於阻障層上；電荷陷阱層覆蓋凹槽的底面；鐵電材料配置於電荷陷阱層上；以及閘極配置於鐵電材料上。 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | 半導體裝置及其製造方法 | zh_TW |
| dc.type | Patents | en_US |
| dc.citation.patentcountry | TWN | en_US |
| dc.citation.patentnumber | 201824542 | en_US |
| Appears in Collections: | Patents | |
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