完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKuo, Ming-Yuen_US
dc.contributor.authorLi, Yaoen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:21:20Z-
dc.date.available2014-12-08T15:21:20Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-9474-3en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/15161-
dc.description.abstractThis paper proposed a high-accuracy prediction scheme and area-efficient CABAC decoder architecture for H. 264 video decoder. To alleviate hardware cost and keep high throughput, we propose the prediction process and optimize the memory system. In particular, simulation results show that the proposed prediction-based CABAC decoder module achieves over 90% hit rate and requires only 16K logic gates with 3,360 bits SRAM by UMC 90 nm technology. The proposed architecture operates on 150 MHz frequency (Max. 249 MHz) for realizing 1080HD video playback at 30 fps, which can achieve Level 5.0 MP in tiny gate count.en_US
dc.language.isoen_USen_US
dc.titleAn Area-efficient High-accuracy Prediction-based CABAC Decoder Architecture for H.264/AVCen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage1960en_US
dc.citation.epage1963en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000297265302068-
顯示於類別:會議論文