H.264/AVC及SVC熵解碼器之分析與設計

Abstract

近年來，由於H.264/AVC較以前的視訊標準有更佳的編碼效率，至今已被廣泛使用在視訊應用系統中。要想實現高解析度畫面即時解碼，熵解碼器的效能需求非常的高。因此，我們需要設計一個高效能的積體電路來加速熵解碼器的解碼速度。 本篇研究提出一個適用於H.264/AVC以及SVC的高產量熵解碼器硬體設計。首先，我們提出一個延遲均衡的雙符號內容適應性變動長度解碼器，並將解碼程序中多餘的解碼步驟省略以加速解碼的進行。工作頻率相較於傳統的設計可提高21%，而整體產量相較於我們之前的設計可提升28.2%。接著，針對H.264/AVC的另一種亂度編碼，我們提出一個以混合式記憶體為架構之高產量內容適應性二元算數解碼器。在整個解碼架構中，我們將語法單元剖析及其解碼進行合併，並提出以混合式記憶體為架構的雙符號平行解碼技術來加速解碼速度。更進一步的，我們利用一個有效率的預測機制以及透過數學上的轉換來提升解碼效能。 基於聯華電子90奈米製程，我們的內容適應性變動長度解碼器的最高工作頻率可達390 MHz，13.88k個邏輯閘。而我們的內容適應性二元算數解碼器的最高工作頻率可達264 MHz，42.37k個邏輯閘。我們的解碼器在節省了48.6%的硬體成本下的產量為每秒451.4百萬個符號，高於其他已被發表的設計。此外，我們將硬體設計拓展到SVC。在工作頻率135 MHz下，我們所提出的熵解碼器可支援3層解析度，最高1920x1080、三層播放頻率、最高每秒60張畫面、以及三層畫面品質的及時解碼。

In recent years, the state-of-the-art video coding standard H.264/AVC which provides better compression efficiency for video images than the earlier standards has been widely adopted in current video application system. To satisfy the heavy performance requirement on real-time H.264/AVC decoding systems especially for large-scale video sequences, VLSI implementation of the entropy decoder is necessary since it dominates the overall decoder system performance. In this thesis, we propose a high-throughput and fully hardwired entropy decoder for H.264/AVC and its scalable extension. First, we present a delay balanced two-level CAVLC decoder with 21% shorter critical path delay in comparison to traditional two-level decoder. Furthermore, a skipping mechanism is adopted to remove unnecessary decoding processes. The overall CAVLC throughput is 28.2% better than our previous design. Second, for the CABAC decoder, we propose a high throughput CABAC decoding design which combines SE parsing and decoding with a new hybrid memory two-symbol parallel decoding technique to accelerate the decoding speed while reducing the hardware cost. Further speedup is achieved to avoid stalls for most of the cases by the prediction-based method. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path delay of two-symbol binary arithmetic decoding procedure by 28%. The proposed entropy decoder is implemented by UMC 90nm technology and experimental results show that our CAVLC decoder can operate at 390 MHz with 13.88k gate count, besides, our CABAC decoder can operate at 264 MHz with 42.37k gate count, and the throughput is 451.4 Mbin/sec, which surpasses previous design with 48.6% hardware cost saving. Furthermore, we extend our entropy decoder towards SVC extension of H.264/AVC. At the working frequency 135 MHz, our proposed entropy decoder can support 3 spatial layers, maximum resolution 1920x1080, 3 temporal layers, maximum frame rate 60 fps, and 3 CGS quality layers real-time SVC decoding.