標題: | Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process |
作者: | Nidhi, Karuna Ker, Ming-Dou Lee, Jian-Hsing Huang, Shao-Chang 交大名義發表 電子工程學系及電子研究所 National Chiao Tung University Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Avalanche ruggedness;avalanche safe-operating-area (A-SOA);current in avalanche (IAV);large-array device (LAD);time in avalanche (tAV);total gate charge (Qg);unclamped inductive switching (UIS) |
公開日期: | 1-七月-2019 |
摘要: | Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I-AV) achieved from themodified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 mu m. |
URI: | http://dx.doi.org/10.1109/TED.2019.2916032 http://hdl.handle.net/11536/152183 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2019.2916032 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 66 |
Issue: | 7 |
起始頁: | 3040 |
結束頁: | 3048 |
顯示於類別: | 期刊論文 |