標題: Asymmetric Wafer-Level Polyimide and Cu/Sn Hybrid Bonding for 3-D Heterogeneous Integration
作者: Lu, Cheng-Hsien
Jhu, Shu-Yan
Chen, Chiao-Pei
Tsai, Bin-Ling
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Application window;Cu/Sn;hybrid bonding;low temperature;polyimide;wafer level
公開日期: 1-Jul-2019
摘要: A low-temperature wafer-level polyimide/metal asymmetric hybrid bonding structure using Cu/Sn metal and low-curing temperature polyimide is proposed in this paper. The Cu/Sn and polyimide can be bonded simultaneously at 250 degrees C. An ultrathin nickel (Ni) buffer layer was used to prevent intermetallic compound (IMC) formation during the deposition process of Sn. Moreover, the asymmetric bonding process could not only optimize the metal and polymer deposition processes but also achieve ultrathin bonding. Furthermore, to solve the issue of surface roughness, the window of polymerto- solder (P/S) thickness ratio from 1.51 to 2.66 was also demonstrated to show the tolerance of polymer hybrid bonding. The specific contact resistances of the bonded structures were generally maintained between 10-7 and 10(-8) Omega-cm(2), which indicate excellent electrical performance. As a result, the proposed wafer-level asymmetric hybrid bonding is a promising method for future 2.5-D and 3-D integration.
URI: http://dx.doi.org/10.1109/TED.2019.2915332
http://hdl.handle.net/11536/152184
ISSN: 0018-9383
DOI: 10.1109/TED.2019.2915332
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 66
Issue: 7
起始頁: 3073
結束頁: 3079
Appears in Collections:Articles