Low temperature bonding technology for 3D integration

doi:10.1016/j.microrel.2011.03.038

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ko, Cheng-Ta	en_US
dc.contributor.author	Chen, Kuan-Neng	en_US
dc.date.accessioned	2014-12-08T15:21:23Z	-
dc.date.available	2014-12-08T15:21:23Z	-
dc.date.issued	2012-02-01	en_US
dc.identifier.issn	0026-2714	en_US
dc.identifier.uri	http://dx.doi.org/10.1016/j.microrel.2011.03.038	en_US
dc.identifier.uri	http://hdl.handle.net/11536/15218	-
dc.description.abstract	3D integration provides a promising solution to achieve system level integration with high function density, small form factor, enhanced transmission speed and low power consumption. Stacked bonding is the key technology to enable the communication between different strata of the 3D integration system. Low temperature bonding approaches are explored in industry to solve the performance degradation issue of the integrated devices. In this paper, various low temperature bonding technologies are reviewed and introduced, as well as the latest developments in world-wide companies and research institutes. The outlook for industrial application is also addressed in the paper. (C) 2011 Elsevier Ltd. All rights reserved.	en_US
dc.language.iso	en_US	en_US
dc.title	Low temperature bonding technology for 3D integration	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1016/j.microrel.2011.03.038	en_US
dc.identifier.journal	MICROELECTRONICS RELIABILITY	en_US
dc.citation.volume	52	en_US
dc.citation.issue	2	en_US
dc.citation.spage	302	en_US
dc.citation.epage	311	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000300190600002	-
dc.citation.woscount	15	-
顯示於類別：	期刊論文

文件中的檔案：

000300190600002.pdf

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。