標題: A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
作者: Huang, Chao-Jen
Lai, Yan-Jiun
Yang, Yu-Jheng Ou
Chen, Hung-Wei
Kuo, Chun-Chieh
Chen, Ke-Horng
Lin, Ying-Hsi
Lin, Shian-Ru
Tsai, Tsung-Yen
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Temperature coefficient (TC) compensation;leakage-based square root compensation (LSRC) technique;low power consumption
公開日期: 1-May-2019
摘要: State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
URI: http://dx.doi.org/10.1109/TCSII.2019.2908284
http://hdl.handle.net/11536/152335
ISSN: 1549-7747
DOI: 10.1109/TCSII.2019.2908284
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 66
Issue: 5
起始頁: 728
結束頁: 732
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