完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Chi-Wei | en_US |
dc.contributor.author | Chen, Yi-Lun | en_US |
dc.contributor.author | Liao, Pei-Chun | en_US |
dc.contributor.author | Lin, Shiau-Pin | en_US |
dc.contributor.author | Wang, Ting-Wei | en_US |
dc.contributor.author | Chung, Ming-Jie | en_US |
dc.contributor.author | Chen, Po-Hung | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.contributor.author | Wu, Chung-Yu | en_US |
dc.date.accessioned | 2019-08-02T02:18:31Z | - |
dc.date.available | 2019-08-02T02:18:31Z | - |
dc.date.issued | 2019-05-01 | en_US |
dc.identifier.issn | 1549-7747 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2019.2909813 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/152336 | - |
dc.description.abstract | This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | High voltage generator | en_US |
dc.subject | BMU | en_US |
dc.subject | buck converter | en_US |
dc.subject | charge pump | en_US |
dc.subject | overstress | en_US |
dc.subject | transistors stacking | en_US |
dc.subject | soft start-up | en_US |
dc.title | An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSII.2019.2909813 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 66 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 788 | en_US |
dc.citation.epage | 792 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000466944200016 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |