低電源電壓之高增益CMOS電荷幫浦式直流/直流穩壓系統積體電路設計

Abstract

本論文研製之新型CMOS電荷幫浦式電路（charge pump circuits）利用電壓增益提升電路（pumping gain increase circuit）實現高效率直流轉直流的升壓輸出。傳統電荷幫浦式電路中，利用MOS開關當作電荷傳輸元件，因受電晶體本身臨界電壓（threshold voltage）的影響，多級串接架構的後級會有嚴重的基板效應（body effect）產生，使得可產生的最高電壓受到限制。文中所介紹的電壓增益提升電路可藉由電路規劃避開基板效應對升壓效率的限制，並且能克服輸出級跨壓損失的問題。因此，此電路的升壓輸出能確實隨著串接級數增加而提高。進一步利用電壓增益提升電路規劃指數升壓架構（exponential-gain structure），不同於傳統串接方式，指數升壓架構能以較少的級數實現更高的升壓輸出。 論文中並針對電阻性負載之電壓增益提升電路提出完整的分析進而推導出等效的電路模型。為了提高此等效模型的實用性，刻意將模型簡單化與規則化，讓使用者可以快速的得到不同級數之等效模型，用以規劃電壓增益提升電路的元件參數，同時亦可預測電路的輸出特性。此外，藉由此等效模型的數學分析，提出穩態時電路升壓輸出的數學式，並由數學式找出針對電容與串接級數最佳化的方式，使能有效的降低晶片面積。此模型與最佳化策略雖然是由電壓增益提升電路推導而來，但同樣適用於其他無內部跨壓損失的改良型電荷幫浦式電路。除此之外，推導出的等效模型可進一步應用於建構具頻率補償的電荷幫浦式穩壓轉換器。論文中將藉由一設計範例，說明如何安排迴授網路以及合適的控制器參數，以達到所需求的電路特性與規格。 論文中以0.35微米互補式金氧半導體混合製程實現電壓增益提升電路，利用一般電池的電壓（1.5V）當作低電壓的輸入電源，模擬並量測實體晶片以驗證電路與指數升壓架構的可行性。此外，等效模型與最佳化的結果同樣透過量測被證實是實用的，而且正確性相當高，在多數情況下，由模型得到的穩態輸出值和晶片量測結果相比，最大誤差約為5%。

This dissertation presents a novel CMOS charge pump circuits (CPCs) utilizing the pumping gain increase (PGI) circuits and the exponential-gain structure with high voltage transfer efficiency to generate boosted output voltages. By employing the PGI circuits, the threshold voltage problem of the MOSFET used as a switch is solved and the limitation of the diode-configured output stage is removed. Thus the boosted output voltage increases more linearly versus the pumping stage number. For the further application of the PGI circuits, an exponential-gain structure is also presented. By using this structure, fewer voltage pump stages are needed to obtain the required output voltage. For 1.5 V supply voltage operation, the simulation and experimental results show that the proposed designs would have good pumping efficiency with a low input supply such as one battery cell. In addition, thorough analysis and a complete equivalent model of the PGI circuit with a resistive load are proposed. Based on the simple analytical model, the characteristics of the PGI circuit can be approximately predicted and the simple equations, which are useful for a pencil and paper design with an acceptable safety margin, can also be found for planning the desired circuit performance in the steady state. Furthermore, an optimized method of the PGI circuit for a resistive load is developed in terms of the stage number and the ratio between pump capacitors as optimization criterions. For 1.5 V supply voltage operation, reliability and accuracy are demonstrated by comparisons between SPICE simulations of the PGI circuit and the corresponding results from the equivalent model. The model also has been validated by means of measurement taken from a test chip, and typically the relative errors are lower than 5 %. Finally, although the derivation of the model was based on PGI circuits, the design strategy can also be equally valid for any other improved CPC designs which are able to eliminate voltage drops within the inner stages and the output stage. Finally, a design procedure of a charge pump regulator based on the equivalent model is illustrated with a design example. The presented charge pump regulator adopts the automatic pumping frequency scheme including a voltage-controlled oscillator, a charge pump circuit, an error detector, and a compensator. By employing the equivalent model, this regulator with a frequency compensation scheme can be implemented and all of the characteristics can be designed through manual and/or computer analysis. The final regulator provides a negative feedback to the pump operation and would insure the output voltage against the variations of loading conditions. From the design example, the accuracy has been demonstrated by comparing the simulation results between the equivalent regulator model and the practical regulator. The primary advantage of this modeling approach is the ease by which the regulator system can be analyzed. This permits that a fast charge pump regulator design would work in practice.