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dc.contributor.authorLiao, Sheng-Huien_US
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.date.accessioned2019-10-05T00:08:42Z-
dc.date.available2019-10-05T00:08:42Z-
dc.date.issued2019-09-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2019.2925273en_US
dc.identifier.urihttp://hdl.handle.net/11536/152825-
dc.description.abstractA 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 mu W from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 x 0.34 mm(2).en_US
dc.language.isoen_USen_US
dc.subjectAnalog-digital conversionen_US
dc.subjectdelta-sigma modulator (DSM)en_US
dc.subjectmultistage noise-shaping (MASH)en_US
dc.subjectswitched-capacitor (SC) circuiten_US
dc.titleA 1-V 175-mu W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniquesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2019.2925273en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume54en_US
dc.citation.issue9en_US
dc.citation.spage2523en_US
dc.citation.epage2531en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000482625000015en_US
dc.citation.woscount0en_US
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