Full metadata record
DC FieldValueLanguage
dc.contributor.authorYeh, M. -S.en_US
dc.contributor.authorLuo, G. -L.en_US
dc.contributor.authorHou, F. -J.en_US
dc.contributor.authorSung, P. -J.en_US
dc.contributor.authorWang, C. -J.en_US
dc.contributor.authorSu, C. -J.en_US
dc.contributor.authorWu, C. -T.en_US
dc.contributor.authorHuang, Y. -C.en_US
dc.contributor.authorHong, T. -C.en_US
dc.contributor.authorChao, T. -S.en_US
dc.contributor.authorChen, B. -Y.en_US
dc.contributor.authorChen, K. -M.en_US
dc.contributor.authorWu, Y. -C.en_US
dc.contributor.authorIzawa, M.en_US
dc.contributor.authorMiura, M.en_US
dc.contributor.authorMorimoto, M.en_US
dc.contributor.authorIshimura, H.en_US
dc.contributor.authorLee, Y. -J.en_US
dc.contributor.authorWu, W. -F.en_US
dc.contributor.authorYeh, W. -K.en_US
dc.date.accessioned2019-10-05T00:08:42Z-
dc.date.available2019-10-05T00:08:42Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2168-6734en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JEDS.2018.2878929en_US
dc.identifier.urihttp://hdl.handle.net/11536/152826-
dc.description.abstractImproved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.en_US
dc.language.isoen_USen_US
dc.subjectALD high-ken_US
dc.subjectin-situ digital ozone treatment (IDOT)en_US
dc.subjectCMOSen_US
dc.subjectFinFETen_US
dc.subjectgermaniumen_US
dc.subjectinvertersen_US
dc.titleGe FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatmenten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JEDS.2018.2878929en_US
dc.identifier.journalIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETYen_US
dc.citation.volume6en_US
dc.citation.issue1en_US
dc.citation.spage1227en_US
dc.citation.epage1232en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000482794200006en_US
dc.citation.woscount0en_US
Appears in Collections:Articles