Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap

Abstract

The impact of EOT (Equivalent Oxide Thickness) scaling, diameter scaling, and interface traps on the performance of gated InAs/Si Hetero pTFET (Tunneling field effect transistor) is investigated. EOT scaling improves SS (SubthresholdSwing) below the thermal limit and on current moderately. Diameter scaling decreases on current and marginally improves SS. The simulation study validates that the transfer characteristics of pTFET in sub-threshold region are completely dominated by thermionic emission of holes and TAT (Trap Assisted Tunneling). This in turn blocks SS to attain < 60 mV/dec. Furthermore, Si/Oxide interface traps minimize the electrostatic gate coupling with channel region additionally deteriorates SS. Interface trap density with different values denotes that sub 2.3k(B)T/q SS can only be realized for interface trap densities D-it < 1 x 10(11) cm(-2)eV(-1) at both InAs/Si and Si/Oxide. Hence this reaffirms the experimental data, that the prerequisite of D-it < 1 x 10(12) cm(-2)eV(-1) for InAs/Si nanowire p-TFET.