標題: | Reconfigurable Radix-2(k)x3 Feedforward FFT Architectures |
作者: | Tsai, Wei-Lun Chen, Sau-Gee Huang, Shen-Jui 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | FFT;MDC;mixed-radix;non-power-of-two |
公開日期: | 1-Jan-2019 |
摘要: | Due to the increasing demand for high-throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi-length FFT processor with the requirement meet has become unprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed-radix 2(k)x3-point feedforward FFT architectures are proposed. It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 1282048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation. |
URI: | http://hdl.handle.net/11536/152956 |
ISBN: | 978-1-7281-0397-6 |
ISSN: | 0271-4302 |
期刊: | 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 0 |
結束頁: | 0 |
Appears in Collections: | Conferences Paper |