標題: An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
作者: Du, Yuan
Du, Li
Gu, Xuefeng
Du, Jieqiong
Wang, X. Shawn
Hu, Boyu
Jiang, Mingzhe
Chen, Xiaoliang
Iyer, Subramanian S.
Chang, Mau-Chung Frank
交大名義發表
National Chiao Tung University
關鍵字: Analog computing engine;artificial neural networks;charge-trap transistors (CTTs);fully connected neural networks (FCNNs)
公開日期: 1-Oct-2019
摘要: An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric, the engine's mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm(2). The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem-classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
URI: http://dx.doi.org/10.1109/TCAD.2018.2859237
http://hdl.handle.net/11536/153049
ISSN: 0278-0070
DOI: 10.1109/TCAD.2018.2859237
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 38
Issue: 10
起始頁: 1811
結束頁: 1819
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