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dc.contributor.authorMa, Junen_US
dc.contributor.authorLiu, Chienen_US
dc.contributor.authorLiu, Wei-Dongen_US
dc.contributor.authorHung, Yu-Wenen_US
dc.contributor.authorFan, Yu-Chien_US
dc.contributor.authorHsu, Hsiao-Hsuanen_US
dc.contributor.authorZheng, Zhi-Weien_US
dc.contributor.authorCheng, Chun-Huen_US
dc.date.accessioned2020-02-02T23:54:36Z-
dc.date.available2020-02-02T23:54:36Z-
dc.date.issued2020-01-01en_US
dc.identifier.issn1536-125Xen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TNANO.2019.2961631en_US
dc.identifier.urihttp://hdl.handle.net/11536/153557-
dc.description.abstractIn this study, we reported a hybrid multi-PNPN channel junctionless field effect transistor (JLFET) with negative capacitance (NC) effect by simulation. By incorporating a ferroelectric HfAlO capacitor with NC effect, an extremely low subthreshold swing of 34 mVdecade, a very high onoff current ratio and a very low driven voltage were achieved in the NC-enhanced hybrid multi-PNPN channel JLFET. This novel device not only improves the on-state current reduction while channel scaling down, but also shows great potential for the next-generation low-power three-dimensional stacked integrated circuit applications.en_US
dc.language.isoen_USen_US
dc.subjectGate-all-arounden_US
dc.subjectjunctionlessen_US
dc.subjectnegative effecten_US
dc.titleCharacteristic Simulation of Hybrid Multilayer Junctionless Field Effect Transistors with Negative Capacitance Effecten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TNANO.2019.2961631en_US
dc.identifier.journalIEEE TRANSACTIONS ON NANOTECHNOLOGYen_US
dc.citation.volume19en_US
dc.citation.spage89en_US
dc.citation.epage93en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000507878200002en_US
dc.citation.woscount0en_US
Appears in Collections:Articles