標題: | Characteristic Simulation of Hybrid Multilayer Junctionless Field Effect Transistors with Negative Capacitance Effect |
作者: | Ma, Jun Liu, Chien Liu, Wei-Dong Hung, Yu-Wen Fan, Yu-Chi Hsu, Hsiao-Hsuan Zheng, Zhi-Wei Cheng, Chun-Hu 電子物理學系 Department of Electrophysics |
關鍵字: | Gate-all-around;junctionless;negative effect |
公開日期: | 1-一月-2020 |
摘要: | In this study, we reported a hybrid multi-PNPN channel junctionless field effect transistor (JLFET) with negative capacitance (NC) effect by simulation. By incorporating a ferroelectric HfAlO capacitor with NC effect, an extremely low subthreshold swing of 34 mVdecade, a very high onoff current ratio and a very low driven voltage were achieved in the NC-enhanced hybrid multi-PNPN channel JLFET. This novel device not only improves the on-state current reduction while channel scaling down, but also shows great potential for the next-generation low-power three-dimensional stacked integrated circuit applications. |
URI: | http://dx.doi.org/10.1109/TNANO.2019.2961631 http://hdl.handle.net/11536/153557 |
ISSN: | 1536-125X |
DOI: | 10.1109/TNANO.2019.2961631 |
期刊: | IEEE TRANSACTIONS ON NANOTECHNOLOGY |
Volume: | 19 |
起始頁: | 89 |
結束頁: | 93 |
顯示於類別: | 期刊論文 |