標題: | Graphene-Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits |
作者: | Yeh, Chao-Hui Liang, Zheng-Yong Lin, Yung-Chang Chen, Hsiang-Chieh Fan, Ta Ma, Chun-Hao Chu, Ying-Hao Suenaga, Kazu Chiu, Po-Wen 材料科學與工程學系 Department of Materials Science and Engineering |
關鍵字: | TMD;2D materials;Schottky barrier;field-effect transistor;integrated circuit;logic gate |
公開日期: | 1-一月-2020 |
摘要: | The most pressing barrier for the development of advanced electronics based on two-dimensional (2D) layered semiconductors stems from the lack of site-selective synthesis of complementary n- and p-channels with low contact resistance. Here, we report an in-plane epitaxial route for the growth of interlaced 2D semiconductor monolayers using chemical vapor deposition with a gas-confined scheme, in which patterned graphene (Gr) serves as a guiding template for site-selective growth of Gr-WS2-Gr and Gr-WSe2-Gr heterostructures. The Gr/2D semiconductor interface exhibits a transparent contact with a nearly ideal pinning factor of 0.95 for the n-channel WS2 and 0.92 for the p-channel WSe2. The effective depinning of the Fermi level gives an ultralow contact resistance of 0.75 and 1.20 k Omega.mu m for WS2 and WSe2, respectively. Integrated logic circuits including inverter, NAND gate, static random access memory, and five-stage ring oscillator are constructed using the complementary Gr-WS2-Gr-WSe2-Gr heterojunctions as a fundamental building block, featuring the prominent performance metrics of high operation frequency (>0.2 GHz), low-power consumption, large noise margins, and high operational stability. The technology presented here provides a speculative look at the electronic circuitry built on atomic-scale semiconductors in the near future. |
URI: | http://dx.doi.org/10.1021/acsnano.9b08288 http://hdl.handle.net/11536/153804 |
ISSN: | 1936-0851 |
DOI: | 10.1021/acsnano.9b08288 |
期刊: | ACS NANO |
Volume: | 14 |
Issue: | 1 |
起始頁: | 985 |
結束頁: | 992 |
顯示於類別: | 期刊論文 |